Display device, and display panel and manufacturing method therefor

ABSTRACT

A display panel includes a driving backplane, a first electrode layer, a pixel definition layer, a light-emitting layer and a second electrode. The first electrode layer is disposed on one side of the driving backplane and includes a plurality of first electrodes. The pixel definition layer is arranged on the side, same as the first electrode layer, of the driving backplane and exposes each of the first electrodes. The pixel definition layer includes a filling layer and a cut-off layer stacked in a direction away from the driving backplane, where the filling layer has a thickness smaller than the first electrode layer. The cut-off layer is provided with a separation slot located outside the first electrodes, and a first cut-off slot is provided on a sidewall of the separation slot. The light-emitting layer covers the cut-off layer and the first electrode layer. The second electrode covers the light-emitting layer.

CROSS REFERENCE TO RELATED APPLICATIONS

This disclosure requires application number filed on Nov. 29, 2021 asPCT/CN2021/133886, Priority Claim to PCT International Applicationentitled “Display Substrate”, 5 The entire content of this PCTInternational Application is hereby incorporated by reference in itsentirety.

TECHNICAL FIELD

This disclosure relates to the field of display technologies, and inparticular, to a display device, a display panel and a method formanufacturing the display panel.

BACKGROUND

With the development of display technologies, display panels have beenwidely used in various electronic devices such as mobile phones torealize image display and touch operation. The OLED (OrganicLight-Emitting Diode) display panel is a relatively common one of them.However, the color gamut of existing display panels still needs to beimproved.

It should be noted that the information disclosed in the backgroundsection above is only used to enhance the understanding of thebackground of this disclosure, and therefore may include informationthat does not constitute prior art known to those of ordinary skill inthe art.

SUMMARY

This disclosure provides a display device, a display panel and a methodfor manufacturing the display panel.

According to an aspect of this disclosure, a display panel is providedand includes:

-   -   a driving backplane;    -   a first electrode layer, disposed on one side of the driving        backplane and including a plurality of first electrodes        distributed at intervals;    -   a pixel definition layer, arranged on the side, same as the        first electrode layer, of the driving backplane and exposing        each of the first electrodes, where the pixel definition layer        includes a filling layer and a cut-off layer stacked in a        direction away from the driving backplane, the filling layer has        a thickness smaller than the first electrode layer and is        located outside the first electrodes, the cut-off layer is        provided with a separation slot located outside the first        electrodes, and a first cut-off slot is provided on a sidewall        of the separation slot;    -   a light-emitting layer, covering the cut-off layer and the first        electrode layer; and    -   a second electrode, covering the light-emitting layer.

In some embodiments of this disclosure, the cut-off layer includes aplurality of insulating layers stacked in the direction away from thedriving backplane, the separation slot exposes the filling layer, thefirst cut-off slot is provided in an insulating layer of the insulatinglayers, and the insulating layer where the first cut-off slot is locatedis any insulating layer other than an insulating layer farthest from thedriving backplane.

In some embodiments of this disclosure, the insulating layers of thecut-off layer include a first insulating layer, a second insulatinglayer and a third insulating layer stacked in sequence along thedirection away from the driving backplane, and the first cut-off slot isprovided in the second insulating layer.

In some embodiments of this disclosure, the sidewall of the separationslot is a slope surface expanding in the direction away from the drivingbackplane.

In some embodiments of this disclosure, a bottom surface of the firstcut-off slot is a slope surface with decreasing depths in the directionaway from the driving backplane.

In some embodiments of this disclosure, a slope angle of the bottomsurface of the first cut-off slot is larger than a slope angle of thesidewall of the separation slot located on the first insulating layer,and larger than a slope angle of the sidewall of the separation slotlocated on the third insulating layer.

In some embodiments of this disclosure, a sum of a slope angle of thebottom surface of the first cut-off slot and a slope angle of thesidewall of the separation slot located on the first insulating layer isnot greater than 90°.

In some embodiments of this disclosure, a sum of a slope angle of thebottom surface of the first cut-off slot and a slope angle of thesidewall of the separation slot located on the third insulating layer isnot greater than 90°.

In some embodiments of this disclosure, an included angle betweenextending surfaces of two sidewalls of the separation slot is an acuteangle.

In some embodiments of this disclosure, the cut-off layer includes acut-off portion and an extension portion, the cut-off portion is locatedoutside the first electrodes, the extension portion is located on asurface of the first electrodes away from the driving backplane and hasa pixel opening exposing the first electrodes, and a sidewall of thepixel opening is a slope surface expanding in the direction away fromthe driving backplane.

In some embodiments of this disclosure, a sum of a slope angle of thesidewall of the pixel opening and a slope angle of the bottom surface ofthe first cut-off slot is not greater than 90°.

In some embodiments of this disclosure, the sidewall of at least a partof the pixel opening is provided with a second cut-off slot.

In some embodiments of this disclosure, a maximum depth of the firstcut-off slot is greater than a maximum depth of the second cut-off slot.

In some embodiments of this disclosure, a part of the third insulatinglayer used for forming a sidewall of the first cut-off slot is inclinedto the driving backplane at a first inclination angle;

-   -   a part of the third insulating layer used for forming a sidewall        of the second cut-off slot is inclined to the driving backplane        at a second inclination angle; and    -   the first inclination angle is greater than the second        inclination angle.

In some embodiments of this disclosure, a planarization portion isformed in a region of the second electrode corresponding to the firstelectrodes, and a groove portion is formed in a region of the secondelectrode corresponding to the separation slot, and a smooth transitionis present between the planarization portion and the groove portion.

In some embodiments of this disclosure, a depth of the groove portion isless than a depth of the separation slot.

In some embodiments of this disclosure, a depth of the groove portion isgreater than the thickness of the filling layer.

In some embodiments of this disclosure, the filling layer is in contactwith a sidewall of the first electrodes.

In some embodiments of this disclosure, the light-emitting layer furtherincludes a plurality of light-emitting sub-layers connected in series,at least one of the light-emitting sub-layers is connected in serieswith an adjacent one of the light-emitting sub-layers through a chargegeneration layer, and a part of the charge generation layercorresponding to the first electrodes is discontinuous with a part ofthe charge generation layer corresponding to the separation slot.

In some embodiments of this disclosure, the filling layer includes afilling insulating layer and a filling conductive layer stacked in thedirection away from the driving backplane, the filling insulating layeris in contact with a sidewall of the first electrodes, and the fillingconductive layer is spaced apart from the sidewall of the firstelectrodes.

In some embodiments of this disclosure, the driving backplane includes apixel area and a peripheral area outside the pixel area, the pixel areais provided with a pixel circuit used for driving light emission of thelight-emitting layer, and the peripheral area is provided with aperipheral circuit;

-   -   the first electrode layer further includes an adapter ring, an        orthographic projection of the adapter ring on the driving        backplane is located in the peripheral area and surrounds the        pixel area, the adapter ring is connected with the peripheral        circuit, the second electrode is connected with the adapter        ring, and the adapter ring is provided with a notch;    -   the filling conductive layer includes a main body and a        connecting portion, the main body is located within the adapter        ring and is spaced apart from the adapter ring; the connecting        portion is connected with the main body, passes out of the        adapter ring through the notch, is spaced apart from the adapter        ring, and is used for receiving an aging voltage signal.

According to an aspect of this disclosure, a method for manufacturingthe display panel as described above includes:

-   -   forming the driving backplane;    -   forming, on a side of the driving backplane, the first electrode        layer including the plurality of first electrodes distributed at        intervals;    -   forming, on the side of the driving backplane provided with the        first electrode layer, the pixel definition layer exposing each        of the first electrodes, where the pixel definition layer        includes a filling layer and a cut-off layer stacked in a        direction away from the driving backplane, the filling layer has        a thickness smaller than the first electrode layer and is        located outside the first electrodes;    -   applying, for a specified period of time, an aging voltage        signal to the filling conductive layer;    -   forming, at the cut-off layer, the separation slot located        outside the first electrodes and the first cut-off slot located        on a sidewall of the separation slot;    -   forming the light-emitting layer covering the cut-off layer and        the first electrode layer; and    -   forming the second electrode covering the light-emitting layer.

According to an aspect of this disclosure, a method for manufacturing adisplay panel is provided and includes:

-   -   forming a driving backplane;    -   forming, on a side of the driving backplane, a first electrode        layer including a plurality of first electrodes distributed at        intervals;    -   forming, on the side of the driving backplane formed with the        first electrode layer, a pixel definition layer exposing each of        the first electrodes, where the pixel definition layer includes        a filling layer and a cut-off layer stacked in a direction away        from the driving backplane, the filling layer has a thickness        smaller than the first electrode layer and is located outside        the first electrodes, the cut-off layer is provided with a        separation slot located outside the first electrodes, and a        first cut-off slot is provided on a sidewall of the separation        slot;    -   forming a light-emitting layer covering the cut-off layer and        the first electrode layer; and    -   forming a second electrode covering the light-emitting layer.

According to an aspect of this disclosure, a display device is providedand includes the display panel according to any one of the aboveembodiments.

It is to be understood that both the foregoing general description andthe following detailed description are exemplary and explanatory onlyand are not restrictive of this disclosure.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are incorporated in and constitute apart of this specification, illustrate embodiments consistent with thedisclosure and together with the description serve to explain theprinciples of the disclosure. Apparently, the drawings in the followingdescription are only some embodiments of this disclosure, and thoseskilled in the art can obtain other drawings according to these drawingswithout creative efforts.

FIG. 1 is a partial cross-sectional view of the display panel accordingto some embodiments of the of this disclosure.

FIG. 2 is a partial cross-sectional view of the display panel accordingto some other embodiments of the of this disclosure.

FIG. 3 is a partial cross-sectional view of some film layers in thedisplay panel according to some embodiments of the of this disclosure.

FIG. 4 is a partial cross-sectional view of some film layers in thedisplay panel according to some other embodiments of the of thisdisclosure.

FIG. 5 is a schematic diagram of a light-emitting unit in the displaypanel according to some embodiments of the of this disclosure.

FIG. 6 is a partial top view of the display panel according to someembodiments of the of this disclosure.

FIG. 7 is a schematic diagram of a light-emitting unit in the displaypanel according to some embodiments of the of this disclosure.

FIG. 8 is a partial cross-sectional view of the display panel accordingto some embodiments of the of this disclosure.

FIG. 9 is a schematic diagram of an adapter ring and a fillingconductive layer in the display panel according to some embodiments ofthe of this disclosure.

DETAILED DESCRIPTION

Example embodiments will now be described more fully with reference tothe accompanying drawings. However, exemplary embodiments may beimplemented in many forms and should not be construed as limited to theembodiments set forth herein. Instead, these embodiments are provided sothat this disclosure will be thorough and complete, and will fullyconvey the concept of the exemplary embodiments to those skilled in theart. The same reference numerals in the drawings denote the same orsimilar structures, and thus their detailed descriptions will beomitted. In addition, the drawings are only schematic representations ofthis disclosure and, thus, are not necessarily drawn to scale.

The terms “a”, “an”, “the”, “said” and “at least one” are used toindicate the presence of one or more elements/components and the like;the terms “including/comprising” and “have” are used to indicate anonexclusive meaning and refer to that there may be additionalelements/components and the like in addition to the listedelements/components and the like. The terms “first”, “second”, “third”and the like are only used as a marker, not a limit on the number ofobjects related thereto.

Any “slope (surface)” in this application represents a straight line inthe section perpendicular to the driving backplane, and a slope angle ofthe “slope” (e.g., α1, α2, β, γ and δ in FIG. 3 ) may be defined as anincluded angle, among included angles between such straight line or itsextended line and a surface where the slope is located, close to thefirst electrode surrounded by the slope. It should be noted that, takinginto account the influence of process errors, the above-mentionedstraight line may not be an absolute straight line, but may be a curveextending roughly along a straight line. There may be multiple tangentlines to the curve, each tangent line may form an included angle withthe surface where the slope is located, and the slope angle of the curvemay be the largest included angle among the included angles, or anaverage value of the included angles.

In the related art, a silicon-based OLED display panel includes adriving backplane and a light-emitting functional layer, where thelight-emitting functional layer is provided on one side of the drivingbackplane and includes a plurality of light-emitting units. Thelight-emitting unit may include one or more light-emitting devicesconnected in series. The light-emitting device may be an organiclight-emitting diode, which may include a first electrode (anode), alight-emitting layer, and a second electrode (cathode) stacked insequence in a direction away from the driving backplane. Thelight-emitting layer may be driven to emit light by applying electricalsignal on the first and second electrodes, while the specificlight-emitting principle of the light-emitting device will not bedescribed in detail here.

In addition, the light-emitting layer of each light-emitting device maybe directly evaporated through FMM (fine metal mask). The light-emittinglayers of respective light-emitting devices are distributed at intervalsto emit light independently, thereby realizing color display. However,due to the limitation of FMM manufacturing process, it is difficult toachieve high PPI (pixels per inch). Therefore, color display may also berealized by combining monochromatic light or white light with colorfilm. Specifically, each light-emitting device shares an identical andcontinuous light-emitting layer, which may emit white light or othermonochromatic light. The color film layer is provided with filter unitscorresponding to the light-emitting units one by one, where a sub-pixelmay be formed by one filter unit and a corresponding light-emittingunit, and a pixel is constituted by a plurality of sub-pixels. Differentcolors of light can pass through different filter units, so thatdifferent sub-pixels may emit different colors of light. A single pixelincludes multiple sub-pixels with different colors. For example, onepixel may include three sub-pixels whose luminescent colors are red,green and blue, respectively. In this way, color display can be realizedby a plurality of pixels.

However, if the light-emitting layer is in a structure of continuous andcomplete layer, electric leakage may be likely to occur between onelight-emitting unit and surrounding light-emitting units, resulting incross-color. Each light-emitting unit may include a plurality oflight-emitting devices connected in series, and respectivelight-emitting devices of the same light-emitting unit share the firstelectrode and the second electrode. There are multiple light-emittingsub-layers between the first electrode and the second electrode, and atleast two adjacent light-emitting sub-layers may be connected in seriesthrough a charge generation layer. Positive charges (holes) may betransferred between two adjacent light-emitting units through the chargegeneration layer. For example, when the light-emitting unitscorresponding to the red filter in the color film layer emits light, dueto the influence of leakage, the light-emitting units corresponding tothe green filter in the color film layer may also emit light, whichreduces the purity of light emitted by a single pixel, decreasing thecolor gamut of the whole display panel.

Embodiments of this disclosure provide a display panel. As shown in FIG.1 and FIG. 2 , the display panel may include a driving backplane BP, afirst electrode layer FE, a pixel definition layer PDL, a light-emittinglayer OL, and a second electrode CAT.

In some embodiments, the first electrode layer FE is disposed on oneside of the driving backplane BP and includes a plurality of firstelectrodes ANO distributed at intervals. The pixel definition layer PDLis arranged on the same side, as the first electrode layer FE, of thedriving backplane BP, and exposes each first electrode ANO. The pixeldefinition layer PDL includes a filling layer PBR and a cut-off layerPCL stacked in a direction away from the driving backplane BP. Athickness of the filling layer PBR is smaller than that of the firstelectrode layer FE, and is located outside the first electrode ANO. Thecut-off layer PCL is provided with a separation slot SES located outsidethe first electrode ANO, and a first cut-off slot CUS1 is provided on asidewall of the separation slot SES. The light-emitting layer OL coversthe cut-off layer PCL and the first electrode layer FE. The secondelectrode CAT covers the light-emitting layer OL.

In the display panel according to some embodiments of this disclosure, alight-emitting unit SUP may be constituted by any one of the firstelectrodes ANO, and the light-emitting layer OL and the second electrodeCAT corresponding thereto. The pixel definition layer PDL may separaterespective light-emitting units SUP to define the range of eachlight-emitting unit SUP. Since the sidewall of the separation slot SESis provided with the first cut-off slot CUS1, even if the light-emittinglayer OL is recessed into the separation slot SES, it is difficult to becontinuously formed in the first cut-off slot CUS1. In other words, atleast part of film layers of the light-emitting layer OL can bediscontinuous at the first cut-off slot CUS1, thereby reducing the riskof electric leakage between adjacent light-emitting units SUP andalleviating cross-color. In addition, the filling layer PBR may be usedto limit the depth of the separation slot SES, and prevent the etchingdepth, when etching the separation slot SES, from being difficult to becontrolled, thereby helping improve the uniformity of different drivingbackplanes BP.

The structure for realizing the display function of the display panelaccording to this disclosure will be described in detail below.

As shown in FIG. 1 and FIG. 2 , the driving backplane BP may include apixel area and a peripheral area, where the peripheral area is locatedoutside the pixel area and may be arranged around the pixel area. Thedriving backplane BP is used to form a driving circuit for driving thelight-emitting unit SUP to emit light, and the driving circuit mayinclude a pixel circuit and a peripheral circuit.

In some embodiments, the number of both the pixel circuit and thelight-emitting unit SUP may be more than one, and at least a part of thepixel circuits is located within the pixel area. The pixel circuit maybe formed in a pixel circuit of 2T1C, 4T1C and the like, as long as itcan drive the light-emitting unit SUP to emit light, which will not bespecially limited here. The pixel circuits have a same number as thefirst electrodes ANO, and is connected to the first electrodes ANO in aone-to-one correspondence, so as to respectively control eachlight-emitting unit SUP to emit light. Herein, nTmC indicates that thepixel circuit includes n transistors (indicated by the letter “T”) and mcapacitors (indicated by the letter “C”). In some embodiments, multiplelight-emitting units SUP may be driven by a single pixel circuit.

The peripheral circuit is located in the peripheral area and connectedwith the pixel circuit. The peripheral circuit may include a lightemission control circuit, a gate driving circuit, a source drivingcircuit, etc., and may also include a power supply circuit connected tothe second electrode CAT for inputting a power supply signal to thesecond electrode CAT. The peripheral circuit may enable thelight-emitting unit SUP to emit light by inputting signals to the firstelectrode ANO and the second electrode CAT through the pixel circuits.

In some embodiments of this disclosure, as shown in FIG. 1 and FIG. 2 ,the driving backplane BP may include a substrate SU, which may be asilicon substrate. The above-mentioned driving circuit may be formed onthe silicon substrate through the semiconductor process. For example,both the pixel circuit and the peripheral circuit may include aplurality of transistors, and a well region WL may be formed in thesilicon substrate through a doping process, where the well region WL isprovided with two doped regions DR distributed at intervals. Take onewell region WL as an example, a gate GATE is provided on one side of thedriving backplane BP, with an orthographic projection of the gate GATEon the driving backplane BP is located between the two doped regions DR;a transistor may be formed by the well region WL and the gate GATE, withthe doped regions DR of the well region WL serving as the firstelectrode and the second electrode of the transistor, respectively, andthe well region WL between the two doped regions DR serving as thechannel region of the transistor.

The driving backplane BP may also include at least one trace layer TLand a planarization layer PLN, where the trace layer TL is provided onone side of the substrate SU, the planarization layer PLN covers thetrace layer TL, and at least one trace layer TL is connected with eachdoped region DR.

For example, as shown in FIG. 1 and FIG. 2 , the number of trace layersTL is two, which are located within the planarization layer PLN. Forexample, the trace layers TL include a first trace layer TL1 and asecond trace layer TL2, where the first trace layer TL1 is provided onone side of the substrate SU, and a part of the planarization layer PLNis provided between the first trace layer TL1 and the substrate SU. Thesecond trace layer TL2 is provided on one side of the first trace layerTL1 away from the substrate SU, and is separated from the first tracelayer TL1 by a part of the planarization layer PLN, and at least apartial region of the second trace layer TL2 is connected with the firsttrace layer TL1.

Each trace layer TL may be formed by a sputtering process. Theplanarization layer PLN may be formed of materials including siliconoxide, silicon oxynitride or silicon nitride, and formed layer by layerthrough multiple deposition and polishing processes. In other words, theplanarization layer PLN may be formed by stacking multiple insulatingfilm layers.

As shown in FIG. 1 and FIG. 2 , the light-emitting units SUP of thedisplay panel are distributed in array on one side of the drivingbackplane BP, for example, on a surface of the planarization layer PLNaway from the substrate SU. Each light-emitting unit SUP may include afirst electrode ANO, a second electrode CAT, and a light-emitting layerOL between the first electrode ANO and the second electrode CAT. Thefirst electrode ANO and the second electrode CAT may both be connectedto the trace layer TL. The light-emitting layer OL may be driven to emitlight by applying a driving signal to the first electrode ANO andapplying a power signal to the second electrode CAT through the drivingbackplane BP.

In order to realize color display, each light-emitting unit SUP may emitlight of the same color and realize color display by cooperating withthe color film layer CF located on one side of the second electrode CATaway from the driving backplane BP. Embodiments of this disclosure isdescribed by taking such solution of color display as an example.

In some embodiments of this disclosure, as shown in FIG. 1 and FIG. 2 ,a plurality of light-emitting units SUP may be formed by the firstelectrode layer FE, the pixel definition layer PDL, the light-emittinglayer OL and the second electrode CAT.

In some embodiments, the first electrode layer FE is disposed on oneside of the driving backplane BP, for example, on a surface of theplanarization layer PLN away from the substrate SU. The first electrodelayer FE may include a plurality of first electrodes ANO distributed atintervals. An orthographic projection of each first electrode ANO on thedriving backplane BP is located in the pixel area. The first electrodesANO are connected to the pixel circuit, with each first electrode ANObeing connected to one pixel circuit.

The first electrode layer FE may be a single-layer or multi-layerstructure, and its material is not particularly limited here.

For example, as shown in FIG. 1 and FIG. 2 , in some embodiments of thisdisclosure, the first electrode ANO may include a first conductive layerANO1, a second conductive layer ANO2 and a third conductive layer ANO3that are stacked in sequence along the direction away from the drivingbackplane BP. In some embodiments, both the first conductive layer ANO1and the third conductive layer ANO3 can be made of metal or metal oxide,such as titanium, titanium nitride, and the like, and the materialsthereof may be the same or different. The second conductive layer ANO2may be made of the same material as of a different material from thefirst conductive layer ANO1 and the third conductive layer ANO3, and hasits resistivity lower than that of the first conductive layer ANO1 andthe third conductive layer ANO3. For example, the material of the secondconductive layer ANO2 may be aluminum.

In some other embodiments of this disclosure, the first electrode ANOmay further include a fourth conductive layer, which may be provided onthe surface of the third conductive layer away from the drivingbackplane BP. The fourth conductive layer may be made of a transparentconductive material such as ITO (Indium Tin Oxide) and the like.

As shown in FIG. 3 and FIG. 4 , the pixel definition layer PDL and thefirst electrode layer FE are provided on the same surface of the drivingbackplane BP, that is, on the surface of the planarization layer PLNaway from the substrate SU. The pixel definition layer PDL exposes eachfirst electrode ANO. Specifically, the pixel definition layer PDL may beprovided with a plurality of pixel openings PO exposing each firstelectrode ANO.

The orthographic projection of any pixel opening PO on the drivingbackplane BP may be located within a corresponding first electrode ANOexposed thereby. In other words, the pixel opening PO is not larger thanthe exposed first electrode ANO. For example, the boundary of the pixelopening PO is located inside the boundary of the exposed first electrodeANO, that is, the area of the pixel opening PO is smaller than the areaof the exposed first electrode ANO.

As shown in FIG. 6 , the shape of the pixel opening PO may be a polygonsuch as rectangle, pentagon, hexagon, but not necessarily a regularpolygon. The pixel opening PO may also be in other shapes, such as anellipse and the like, which are not particularly limited here.

As shown in FIG. 1 and FIG. 2 , the light-emitting layer OL covers thepixel definition layer PDL and the first electrode ANO, and the areawhere the light-emitting layer OL and the first electrode ANO arestacked is used to form a light-emitting unit SUP. In other words,respective light-emitting units SUP may share the same light-emittinglayer OL, and the parts of the light-emitting layer OL that are stackedon different first electrodes ANO belong to different lighting unitsSUP. In addition, 20, since respective light-emitting units SUP sharethe light-emitting layer OL, different light-emitting units SUP can emitlight of the same color.

In some embodiments of this disclosure, as shown in FIG. 1 , FIG. 2 andFIG. 7 , the light-emitting unit SUP may include a plurality oflight-emitting devices LD connected in series. Each light-emitting unitSUP includes a first electrode ANO, a second electrode CAT and aplurality of light-emitting sub-layers OLP between the first electrodeANO and the second electrode CAT. Respective light-emitting devices LDof the same light-emitting unit SUP may share the same first electrodeANO and the same second electrode CAT, that is, the same light-emittingunit SUP may have only one first electrode ANO and one second electrodeCAT.

For example, as shown in FIG. 1 , FIG. 2 and FIG. 7 , the light-emittinglayer OL may include multiple light-emitting sub-layers OLP connected inseries along the direction away from the driving backplane BP, and atleast one light-emitting sub-layer OLP is connected in series with anadjacent light-emitting sub-layer OLP through the charge generationlayer CGL. When the electric signal is applied to the first electrodeANO and the second electrode CAT, each light-emitting sub-layer OLP canemit light, and different light-emitting sub-layers OLP can be used toemit light of different colors.

Furthermore, as shown in FIG. 7 , any light-emitting sub-layer OLP mayinclude a hole injection layer HIL, a hole transport layer HTL, alight-emitting material layer EML, an electron transport layer ETL andan electron injection layer EIL distributed in the direction away fromthe driving backplane BP. The specific luminescence principle will notbe described in detail here.

In some embodiments, the numbers of the hole injection layer HIL, holetransport layer HTL, electron transport layer ETL and electron injectionlayer EIL are not particularly limited here, and adjacent light-emittingsub-layers OLP may share one or more of the hole injection layer HIL,hole transport layer HTL, electron transport layer ETL and electroninjection layer EIL. Moreover, the charge generation layer CGL may beprovided between at least two adjacent light-emitting sub-layers OLP, sothat the two light-emitting sub-layers OLP are connected in series.

In some embodiments of this disclosure, as shown in FIG. 7 , thelight-emitting layer OL may include three light-emitting sub-layers OLPwith different colors, that is, the first light-emitting sub-layer OLPrthat emits red light, the second light-emitting sub-layer OLPg thatemits green light, and the third light-emitting sub-layer OLPb thatemits blue light. The first light-emitting sub-layer OLPr, the secondlight-emitting sub-layer OLPg and the third light-emitting sub-layerOLPb may emit light at the same time, so as to emit white light. In someembodiments, the first light-emitting sub-layer OLPr and the secondlight-emitting sub-layer OLPg share the hole injection layer HIL, thehole transport layer HTL1, the electron transport layer ETL2 and theelectron injection layer EIL, and the light-emitting material layerG-EML of the second light-emitting sub-layer OLPg is provided on asurface of the light-emitting material layer R-EML of the firstlight-emitting sub-layer OLPr away from the driving backplane BP, sothat the first light-emitting sub-layer OLPr and the secondlight-emitting sub-layer OLPg are directly connected in series withoutusing or providing the charge generation layer. The charge generationlayer CGL may be provided on the surface of the second light-emittingsub-layer OLPg away from the driving backplane BP. The thirdlight-emitting sub-layer OLPb shares the electron injection layer EILwith the first light-emitting sub-layer OLPr and the secondlight-emitting sub-layer OLPg, the hole injection layer HIL2 of thethird light-emitting sub-layer OLPb is disposed on the surface of thecharge generation layer CGL away from the driving backplane BP, and thehole transport layer HTL2 and the hole transport layer HTL3 of the thirdlight-emitting sub-layer OLPb are stacked in sequence on the side of thecharge generation layer CGL away from the driving backplane BP, so thatthe charge generation layer CGL connects the third light-emittingsub-layer OLPb in series with the second light-emitting sub-layer OLPgand the first light-emitting sub-layer OLPr. In addition, a hole fillinglayer HBL may be provided between the electron transport layer HYL andthe light-emitting material layer BEML of the third light-emittingsub-layer OLPb.

The structure of the light-emitting layer OL described above is only anexample and does not constitute a limitation to its film layers. It mayinclude only two or more than three light-emitting sub-layers OLP, orinclude only one light-emitting sub-layer OLP, as long as it cancooperate with the color film layer CF to realize color display.

As shown in FIG. 1 , FIG. 2 and FIG. 7 , the second electrode CAT coversthe light-emitting layer OL, and the orthographic projection of thesecond electrode CAT on the driving backplane BP may cover the pixelarea and extend into the peripheral area. Respective light-emittingunits SUP may share the same second electrode CAT. Light emission of thelight-emitting layer OL may be controlled by controlling the voltages ofthe power signal input to the second electrode CAT and the drivingsignal input to the first electrode ANO.

As shown in FIG. 1 and FIG. 2 , the display panel may further include acolor film layer CF, which may be disposed on the side of the secondelectrode CAT away from the driving backplane BP, and includes aplurality of filter units CFU. Respective first electrodes ANO andfilter units CFU are arranged opposite to each other one by one in thedirection perpendicular to the driving backplane BP. In other words, theorthographic projection of a filter unit CFU on the driving backplane BPat least partially coincides with a first electrode ANO. Each filter CFUincludes filter CFUs of at least three colors, for example, a filterunit CFU for passing red light, a filter unit CFU for passing greenlight, and a filter unit CFU for passing blue light. After the lightemitted by each light-emitting unit SUP is filtered by the filter unitCFU, monochromatic light of different colors can be obtained, therebyrealizing color display. In some embodiments, a sub-pixel may beconstituted by a filter unit CFU and its corresponding light-emittingunit SUP, and the color of light emitted by any sub-pixel is the colorof the light transmitted by its filter unit CFU. A pixel may beconstituted by a plurality of sub-pixels, and respective sub-pixels inthe same pixel emit light of different colors.

The color film layer CF may further include a light-shielding portionfor separating the filter units CFU, the light-shielding portion isopaque and shields the area between two light-emitting units SUP. Thefilter units CFU may be arranged at intervals by using a light-shieldingmaterial directly. Alternatively, as shown in FIG. 1 and FIG. 2 , insome embodiments of this disclosure, adjacent filter units CFU may bestacked at the area corresponding to two adjacent light-emitting unitsSUP, with the colors of the light transmitted by them being different,so that the stacked area is opaque.

In addition, in some embodiments of this disclosure, on the basis thatthe light-emitting layer OL emits white light, in order to improve thebrightness of the screen, the color film layer CF may further include atransparent portion. In the direction perpendicular to the substrate,the transparent portion may be provided opposite to the light-emittingunit SUP, so that the color film layer CF can also transmit white light,thereby improving the brightness by the white light.

In order to improve the light extraction efficiency, a light extractionlayer may be covered on the side of the second electrode CAT away fromthe driving backplane BP to improve brightness. Furthermore, the lightextraction layer may directly cover the surface of the second electrodeCAT away from the driving backplane BP.

In order to facilitate the connection of the second electrode CAT withthe driving circuit, in some embodiments of this disclosure, the firstelectrode layer FE further includes an adapter ring. The orthographicprojection of the adapter ring on the driving backplane BP is located inthe peripheral area. The adapter ring may be connected with theperipheral circuit, and surround the pixel area. The second electrodeCAT may be connected with the adapter ring, so that the second electrodeCAT can be connected with the peripheral circuit through the adapterring, and the driving signal can be applied by the peripheral circuit tothe second electrode CAT. The pattern of the adapter ring may be thesame as that of the first electrode ANO in the pixel area, so as toimprove the uniformity of pattern of the first electrode layer FE.

In some embodiments of this disclosure, as shown in FIG. 1 and FIG. 2 ,the display panel of this disclosure may further include a firstencapsulation layer TFE1, which may be disposed on the side of thesecond electrode CAT away from the driving backplane BP, located betweenthe color film layer CF and the second electrode CAT, and used to blockthe erosion of external water and oxygen. The first encapsulation layerTFE1 may be a single-layer or multi-layer structure. For example, thefirst encapsulation layer TFE1 may include a first encapsulationsub-layer, a second encapsulation sub-layer, and a third encapsulationsub-layer stacked in sequence along the direction away from the drivingbackplane BP. In some embodiments, materials of the first encapsulationsub-layer and the second encapsulation sub-layer may be inorganicinsulating materials such as silicon nitride and silicon oxide, and thesecond encapsulation sub-layer may be formed by the ALD (Atomic LayerDeposition) process; the material of the third encapsulation sub-layermay be an organic material, and it may be formed by the MLD (MolecularLayer Deposition) process. Alternatively, the first encapsulation layerTFE1 may also adopt other structures, and the structure of the firstencapsulation layer TFE1 is not particularly limited here.

In addition, in some embodiments of this disclosure, as shown in FIG. 1and FIG. 2 , the display panel of this disclosure may further include asecond encapsulation layer TFE2, which may cover the surface of thecolor film layer CF away from the driving backplane BP, so as to achieveplanarization, to facilitate covering the transparent cover, and toimprove the encapsulation effect and further block water and oxygen. Thesecond encapsulation layer may be a single-layer or multi-layerstructure, and may include inorganic materials such as silicon nitrideand silicon oxide, or organic materials, and the structure of the secondencapsulation layer is not particularly limited here.

In addition, the display panel may also include the transparent cover,which may cover the side of the second encapsulation layer TFE2 awayfrom the driving backplane BP. The transparent cover may be asingle-layer or multi-layer structure, and its material is notspecifically limited.

Based on the above analysis of related art, since respectivelight-emitting units SUP share the light-emitting layer OL, the carriers(e.g., holes) of a light-emitting unit SUP may move to otherlight-emitting units SUP, especially to its adjacent light-emittingunits SUP, through the charge generation layer CGL. In other words,electric leakage occurs, which may affect the purity of light emissionand cause cross-color. Therefore, as shown in FIG. 1 and FIG. 2 , theseparation slot SES may be provided in the cut-off layer PCLSL, and afirst cut-off slot CUS1 may be opened on a side wall of the separationslot SES. Owing to the restriction of the first cut-off slot CUS1, whenthe light-emitting layer OL is formed, it is difficult to be continuousat the first cut-off slot CUS1, and thus disconnected at the separationslot SES, so as to prevent carriers from moving between thelight-emitting units SUP, thereby avoiding cross-color caused byelectric leakage. Further, in order to limit the depth of the separationslot SES and prevent it from extending into the driving backplane BP, aswell as prevent the depth difference of different display panels frombeing too large, the etching depth when forming the filling layer PBRmay be limited by the filling layer PBR. In other words, the depth ofthe separation slot SES is limited to the filling layer PBR, which isbeneficial to improve the uniformity of the structure of differentdriving backplanes BP.

The solution directed to the cross-color problem of the display panelaccording to this disclosure will be described in detail below.

As shown in FIG. 1 and FIG. 2 , in order to achieve the above purpose,the pixel definition layer PDL may include at least two layers, i.e., afilling layer PBR and a cut-off layer PCL, and the filling layer PBR maybe directly stacked on the driving backplane BP. The filling layer PBRand the first electrode layer FE may be arranged on the same surface ofthe planarization layer PLN away from the substrate. The filling layerPBR is located outside the first electrode layer FE, and separates therespective first electrodes ANO. In other words, the filling layer PBRmay be regarded as a film layer with multiple through holes, withrespective first electrodes ANO may be arranged in the through holes inone-to-one correspondence. In addition, in order to provide enoughrecessed space for the separation slot SES on the cut-off layer PCL, thethickness of the filling layer PBR is smaller than that of the firstelectrode ANO. For example, for the first electrode ANO including thefirst conductive layer ANO1, the second conductive layer ANO2 and thethird conductive layer ANO3, the thickness of the filling layer PBR maybe greater than that of the first conductive layer ANO1, but less than asum of the thickness of the second conductive layer ANO2 and thethickness of the first conductive layer ANO1. In other words, thesurface of the filling layer PBR away from the driving backplane BP islocated between the surface of the second conductive layer ANO2 awayfrom the driving backplane BP and the first conductive layer ANO1. Inaddition, the material of the filling layer PBR may be inorganicinsulating materials such as silicon oxide and silicon nitride.Alternatively, other insulating materials may also be used. Moreover,the filling layer PBR may be in contact with the sidewall of the firstelectrode ANO, that is, the sidewall of the through hole is attached tothe sidewall of the first electrode ANO inside the through hole. Sincethe material of the filling layer PBR is an insulating material, it willnot be electrically connected with the first electrode ANO, therebyavoiding short-circuit between the adjacent first electrodes ANO.

As shown in FIG. 1 and FIG. 2 , the cut-off layer PCL may be stacked onthe surface of the filling layer PBR away from the driving backplane BP,and expose respective first electrodes ANO. A sum of the thickness ofthe cut-off layer PCL and the filling layer PBR may be greater than thethickness of the first electrode layer FE.

In some embodiments of this disclosure, as shown in FIG. 3 , a partialregion of the cut-off layer PCL may extend to the surface of the firstelectrode ANO away from the driving backplane BP, but does notcompletely cover the first electrode ANO. Correspondingly, the cut-offlayer PCL may include a cut-off portion PDLc and an extension portionPDLe. The cut-off portion PDLc may be located outside the firstelectrode ANO, the extension portion PDLe may be located on the surfaceof the first electrode ANO away from the driving backplane BP, and theremay be an overlapping area between the orthographic projections of thepixel definition layer PDL and the first electrode ANO on the drivingbackplane BP. The pixel opening PO may be opened in the extensionportion PDLe to expose the first electrode ANO. Since the thickness ofthe first electrode ANO is greater than that of the filling layer PBR,the cut-off layer PCL, when extending from the cut-off portion PDLc tothe extension portion PDLe, may need to be raised in height (likeclimbing a slope). In other words, the surface of the extension portionPDLe away from the first electrode ANO is located at a side, facing awayfrom the driving backplane BP, of the surface of the cut-off portionPDLc away from the driving backplane BP. In addition, in someembodiments, the side wall of the pixel opening PO may be the slopeexpanding in a direction away from the driving backplane BP.

In some other embodiments of this disclosure, the cut-off layer PCL maynot include the extension portion PDLe, but only include the cut-offportion PDLc, and the cut-off portion PDLc may separate the respectivefirst electrodes ANO. In other words, boundaries of the projections ofthe cut-off portion PDLc and the filling layer PBR on the drivingbackplane BP may overlap with each other. The pixel opening PO may be avia hole penetrating the cut-off portion PDLc and the filling layer PBR,and there is no overlapping region between the orthographic projectionsof the pixel definition layer PDL and the first electrode ANO on thedriving backplane BP.

As shown in FIG. 1 and FIG. 2 , the cut-off layer PCL is provided withthe separation slot SES, and the separation slot SES is located outsidethe first electrode ANO, which may be an annular slot surrounding thefirst electrode ANO, with each first electrode ANO may be surrounded bya separation slot SES. Separation slots SES surrounding two adjacentfirst electrodes ANO may share a partial area, so that there may be onlyone separation slot SES between two adjacent first electrodes ANO, withone side wall of the separation slot SES surrounding outside anelectrode, and the two side walls of the separation slot SES.Alternatively, separation slots SES may also be opened independentlysurrounding two adjacent first electrodes ANO without any shared part.In addition, the side wall of the separation slot SES may be a slopeexpanding in the direction away from the driving backplane BP, that is,the distance between two side walls of the separation slot SES increasesgradually along the direction away from the driving backplane BP, andthe slope angle of the side walls of the separation slot SES is lessthan or equal to 90°.

As shown in FIG. 1 and FIG. 2 , the side wall of the separation slot SESis provided with a first cut-off slot CUS1, and the first cut-off slotCUS1 may recess from the side wall of the separation slot SES to thefirst electrode ANO surrounded by the separation slot SES, with therecessing direction being its depth direction. The depth of the firstcut-off slot CUS1 may be smaller than the distance between the side wallwhere it is located and the first electrode ANO, that is to say, thefirst cut-off slot CUS1 does not penetrate the cut-off layer PCL in itsdepth direction.

As shown in FIG. 1 and FIG. 2 , the first cut-off slot CUS1 may extendalong the extending direction of the separation slot SES, therebyforming an annular slot on the sidewall of the separation slot SES. Thelight-emitting layer OL covers the cut-off layer PCL and the firstelectrode layer FE, and is recessed into the separation slot SES.However, due to the existence of the first cut-off slot CUS1, the chargegeneration layer CGL or other film layers of the light-emitting layer OLmay be difficult to be formed within the first cut-off slot CUS1 and,instead, tend to be disconnected on the side wall of the separation slotSES. For example, a part of the charge generation layer CGLcorresponding to the first electrode ANO is disconnected from a partthereof corresponding to the separation slot SES, thereby avoidingcross-color between adjacent light-emitting units SUP.

In order to ensure the cut-off effect, first cut-off slots CUS1 may beprovided on both sides of the separation slot SES, and one or more firstcut-off slots CUS1 may be opened on a single side wall thereof. If aplurality of first cut-off slots CUS1 are provided on one side wall,respective first cut-off slots CUS1 may be distributed at intervalsalong the direction away from the driving backplane BP.

The specific manner of forming the first cut-off slot CUS1 will bedescribed in detail below.

As shown in FIG. 1 and FIG. 2 , in some embodiments of this disclosure,the cut-off layer PCL includes multiple insulating layers stacked in thedirection away from the driving backplane BP. The material of eachinsulating layer may be insulating inorganic materials such as siliconoxide, silicon nitride, and the like, there is no special limitationhere, and the materials of different insulating layers are the same ordifferent. The separation slot SES may expose the filling layer PBR,that is, the separation slot SES penetrates respective insulatinglayers. The first cut-off slot CUS1 may be opened on an insulatinglayer, and the insulating layer where it is located is any insulatinglayer except the insulating layer farthest from the driving backplaneBP. For example, the number of insulating layers of the cut-off layerPCL may be three, that is, the first insulating layer CL1, the secondinsulating layer CL2 and the third insulating layer CL3 sequentiallystacked along the direction away from the driving backplane BP, wherethe first cut-off slot CUS1 may be opened in the second insulating layerCL2. As shown in FIG. 3 , the separation slot SES penetrates through thefirst insulating layer CL1 and the third insulating layer CL3, thesidewall of a part of the separation slot SES located in the firstinsulating layer CL1 may be a slope surface expanding in the directionaway from the driving backplane BP, and the side wall of a part of theseparation slot SES located in the third insulating layer CL3 may be aslope surface expanding in the direction away from the driving backplaneBP, with the slope angles of above two slope surfaces, α1 and α2, beingneither greater than 900 and, optionally, being the same.

The material of the insulating layer, where the first cut-off slot CUS1is to be formed, may be different from that of other insulating layers.When the first cut-off slot CUS1 is formed, the separation slot SES andthe first cut-off slot CUS1 may be formed based on different degrees ofetching when different materials are etched by the etching process.Alternatively, other processed may also be adopted, as long as theseparation slot SES and the first cut-off slot CUS1 can be formed.

As shown in FIG. 3 , two side walls of the first cut-off slot CUS1 maybe distributed along the direction away from the driving backplane BP,there is a bottom surface between the two side walls, and the bottomsurface surrounds outside the first electrode ANO. The bottom surfacemay be a slope surface along which the depth of the first cut-off slotCUS1 is reduced in the direction away from the driving backplane BP. Inother words, the bottom surface of the first cut-off slot CUS1surrounding the first electrode ANO is an annular surface expanding inthe direction away from the driving backplane BP, that is, the slopeangle β of the bottom surface of the first cut-off slot CUS1 is greaterthan 90°. Alternatively, the bottom surface of the first cut-off slotCUS1 may also be perpendicular to the driving backplane BP.

As shown in FIG. 3 , the slope angle β of the bottom surface of thefirst cut-off slot CUS1 is greater than the slope angle α1 of a sidewall of the separation slot SES located in the first insulating layerCL1, and greater than the slope angle α2 of a side wall of theseparation slot SES located in the third insulating layer CL3. Inaddition, a sum of the slope angle β of the bottom surface of the firstcut-off slot CUS1 and the slope angle α1 of the sidewall of theseparation slot SES located in the first insulating layer CL1 is notgreater than 90°, for example, it may be 50°, 60° or the like. Moreover,a sum of the slope angle β of the bottom surface of the first cut-offslot CUS1 and the slope angle α2 of the sidewall of the separation slotSES located in the third insulating layer CL3 is not greater than 90°.In some other embodiments of this disclosure, slope angles of the twoslope surfaces may be different. Furthermore, as shown in FIG. 3 , a sumof a slope angle δ of the sidewall of the pixel opening PO and the slopeangle R of the bottom surface of the first cut-off slot CUS1 may be notless than 90°.

In some embodiments of this disclosure, one side wall of the firstcut-off slot CUS1 is located in the first insulating layer CL1, whilethe other side wall thereof is located in the third insulating layerCL3, and an included angle 7 between extension surfaces of the two sidewalls of the separation slot SES is an acute angle, so that the sidewalllocated in the third insulating layer CL3 is shorter than the sidewalllocated in the first insulating layer CL1. In other words, a suspendedpart of the third insulating layer CL3 corresponding to the firstcut-off slot CUS1 is shorter than a part of the first insulating layerCL1 corresponding to the first cut-off slot CUS1. In addition to cuttingoff the light-emitting layer OL, a risk that the third insulating layerCL3 is broken due to the first cut-off slot CUS1 can be reduced.

In some embodiments of this disclosure, as shown in FIG. 2 and FIG. 3 ,for the pixel definition layer PDL having the extension portion PDLe, asecond cut-off slot CUS2 may be provided on the side wall of at least apart of the pixel openings PO. As the pixel opening PO is located in theextension portion PDLe, the second cut-off slot CUS2 is actually openedon the extension portion PDLe. Accordingly, the charge generation layerCGL may be disconnected by the second cut-off slot CUS2, thereby furtherpreventing cross-color. For the specific implementation of the secondcut-off slot CUS2, that of the first cut-off slot CUS1 may be referred.For example, the second cut-off slot CUS2 is opened in the secondinsulating layer CL2, so that the third insulating layer CL3 issuspended at the second cut-off slot CUS2. Moreover, in order to preventthe extension portion PDLe from causing a large shield to the firstelectrode ANO, an area of the extension portion PDLe is relativelysmall. Correspondingly, it may be necessary to limit the depth of thesecond cut-off slot CUS2, so that the maximum depth of the first cut-offslot CUS1 is greater than the maximum depth of the second cut-off slotCUS2. In addition to ensuring that the second cut-off slot CUS2 can cutoff at least part of the film layers of the light-emitting layer OL, thedepth thereof can be prevented from being sufficiently large to cut offthe extension PDLe, which is beneficial to maintain the stability of thestructure.

Further, the second cut-off slot CUS2 may be formed on the extensionportion PDLe of each first electrode ANO; and the second cut-off slotCUS2 may also be formed on the extension portion PDLe of the firstelectrode ANO of a specific light-emitting unit SUP. For example, in thecolor film layer CF, the range of the blue filter CFU is larger than therange of the red and green filter CFU, that is, the orthographicprojection of the blue filter CFU on the driving backplane BP has agreater area than the orthographic projection of the red and greenfilter CFU on the driving backplane BP. So the second cut-off slot CUS2may be provided on the sidewall of the pixel opening PO of the bluesub-pixel, rather than being provided in the pixel opening PO of the redand green sub-pixels.

In some embodiments of this disclosure, as shown in FIG. 4 , for thefirst cut-off slot CUS1 and the second cut-off slot CUS2 formed on thesecond insulating layer CL2, a part of the third insulating layer CL3used to form the sidewall of the first cut-off slot CUS1 is inclined tothe driving backplane BP, and the inclination angle is a firstinclination angle θ1. In other words, the two sidewalls of the firstcut-off slot CUS1 may not be parallel to each other. A part of the thirdinsulating layer CL3 used to form the sidewall of the second cut-offslot CUS2 is inclined to the driving backplane BP, and the inclinationangle is the second inclination angle θ2. In other words, the two sidewalls of the second cut-off slot CUS2 may not be parallel to each other.In some embodiments, the first inclination angle θ1 may be greater thanthe second inclination angle θ2, that is, compared with the area of thethird insulating layer CL3 in the second cut-off slot CUS2, the thirdinsulating layer CL3 is more inclined in the area of the first cut-offslot CUS1.

As shown in FIG. 5 , based on the topography of the above-mentionedpixel definition layer PDL and light-emitting layer OL, a planarizationportion CATp may be formed in a region of the second electrode CATcorresponding to the first electrode ANO, and a groove portion may beformed in a region thereof corresponding to the separation slot SES. Asmooth transition may be present at the connection between the grooveportion CATg and the planarization portion CATp, so as to avoid sharpcorners of the second electrode CAT. The separation slot SES is filledby the light-emitting layer OL, such that the depth of the grooveportion CATg of the second electrode CAT is smaller than that of theseparation slot SES. In addition, the depth of the groove portion CATgmay be greater than the thickness of the filling layer PBR.

In addition, in some embodiments of this disclosure, as shown in FIG. 8and FIG. 9 , for the light-emitting layer OL provided in the entirelayer, that is, in the case where respective light-emitting units SUPshare an entire light-emitting layer OL, aging treatment may beperformed on the light-emitting layer OL between the light-emittingunits SUP, so as to increase an impedance of the light-emitting layer OLin the aging area, thereby reducing the ability of the light-emittinglayer OL to conduct laterally, and weakening the leakage betweenadjacent light-emitting units SUP.

For example, the filling layer PBR may include a filling insulatinglayer PBRi and a filling conductive layer PBRc stacked in the directionaway from the driving backplane.

In some embodiments, the material of the filling insulating layer PBRmay be insulating materials such as silicon nitride and silicon oxide,and the filling insulating layer PBRi is in contact with the sidewall ofthe first electrode ANO. The material of the filling conductive layerPBRc may be metal or other conductive materials, and is spaced apartfrom the sidewall of the first electrode ANO, so as to be insulated fromthe first electrode ANO. In this case, the bottom of the separation slotSES may not be flat, it may include a surface, that is not covered bythe filling conductive layer PBRc, of the filling insulating layer PBRaway from the driving backplane BP, and may also include a surface ofthe filling conductive layer PBRc away from the driving backplane BP.The first cut-off slot CUS1 is located on the side of the fillingconductive layer PBRc away from the driving backplane BP, that is, abovethe filling conductive layer PBRc. The cut-off layer PCL may cover thefilling conductive layer PBRc, or may also be located outside thefilling conductive layer PBRc, as long as it does not affect theformation of the first cut-off slot CUS1.

The first electrode layer FE may also include an adapter ring CR, theorthographic projection of the adapter ring CR on the driving backplaneBP is located in the peripheral area and surrounds the pixel area. Theadapter ring CR is connected to the peripheral circuit, and the secondelectrode CAT is connected to the adapter ring CR. As to the adapterring CR, the forgoing embodiments may be referred to, which will not berepeated here. The adapter ring CR is provided with a notch CRh fordisconnecting it.

The filling conductive layer PBRc may include a main body PBRc1 and aconnecting portion PBRc2. The main body PBRc is located within theadapter ring CR and spaced apart from the adapter ring CR, so as to beinsulated from the adapter ring CR. The connecting portion PBRc2 isconnected with the main body PBRc1, passes out of the adapter ring CRthrough the notch CRh, is spaced apart from the adapter ring CR. Inother words, the connecting portion PBRc2 does not contact the notch CRhand, thus, is insulated from the adapter ring CR. The main body PBRc1and the connecting portion PBRc2 may be integrally formed and may beformed at the same time.

The connection portion PBRc2 may be connected with the peripheralcircuit for receiving the aging voltage signal, so as to cooperate withthe second electrode CAT to apply the aging voltage to thelight-emitting layer OL, so that the light-emitting layer OL is aged inthe area corresponding to the main body PBRc1, with the impedance beingincreased. The aging voltage may depend on the material and thickness ofthe light-emitting layer OL, for example, may be greater than 8 v, 15 v,20 v, 30 v, and the like, which is not particularly limited here, aslong as the light-emitting material OL can be aged. In addition, theduration of the aging voltage may also be controlled to a specifiedduration, that is, the duration of the aging voltage signal is aspecified duration. The specified duration may not be greater than 10seconds and, alternatively, may be longer, as long as the light-emittingmaterial OL can be aged.

Embodiments of this disclosure further provide a method formanufacturing the display panel. The display panel may be the displaypanel in any of the above embodiments, and its structure will not bedescribed in detail here. The manufacturing method may include stepsS110-S140.

In step S110, a driving backplane is formed.

In step S120, a first electrode layer, including a plurality of firstelectrodes distributed at intervals, is formed on one side of thedriving backplane.

In step S130, a pixel definition layer, exposing each first electrode,is formed on the side of the driving backplane on which the firstelectrode layer is formed, where the pixel definition layer includes afilling layer and a cut-off layer stacked in a direction away from thedriving backplane, the filling layer has a thickness smaller than thefirst electrode layer and is located outside the first electrodes; thecut-off layer is provided with a separation slot located outside thefirst electrodes, and the side wall of the separation slot is providedwith a first cut-off slot.

In step S140, a light-emitting layer covering the cut-off layer and thefirst electrode layer is formed.

In step S150, a second electrode covering the light-emitting layer isformed.

Based on the above-mentioned display panel provided with the fillinginsulating layer PBRi and filling conductive layer PBRc, in someembodiments of this disclosure, the manufacturing method may includesteps S110-S170.

In step S110, a driving backplane is formed.

In step S120, a first electrode layer, including a plurality of firstelectrodes distributed at intervals, is formed on one side of thedriving backplane.

In step S130, a pixel definition layer, exposing each first electrode,is formed on the side of the driving backplane on which the firstelectrode layer is formed, where the pixel definition layer includes afilling layer and a cut-off layer stacked in a direction away from thedriving backplane, the filling layer has a thickness smaller than thefirst electrode layer and is located outside the first electrodes.

In step S140, an aging voltage signal is applied to the fillingconductive layer for a specified period of time.

In step S150, a separation slot located outside the first electrodes anda first cut-off slot located on the side wall of the separation slot areformed in the cut-off layer.

In step S160, a light-emitting layer covering the cut-off layer and thefirst electrode layer is formed.

In step S170, a second electrode covering the light-emitting layer isformed.

Since details of the structure involved in each step of theabove-mentioned manufacturing method have been described in detail inthe forgoing embodiments of the display panel, the details andbeneficial effects thereof will not be described in detail here.

It should be noted that although various steps of the manufacturingmethod in this disclosure are described in a specific order in thedrawings, this does not require or imply that these steps must beperformed in this specific order, or that all shown steps must beperformed to achieve the desired result. Additionally or alternatively,certain steps may be omitted, multiple steps may be combined into onestep for implementation, and/or one step may be decomposed into multiplesteps for implementation.

Embodiments of this disclosure further provide a display device, whichmay include the display panel in any of the above embodiments. Thespecific structure and beneficial effects of the display panel have beendescribed in detail in the forgoing embodiments of the display panel,and will not be described in detail here. The display device accordingto this disclosure may be used in electronic devices with image displayfunctions, such as watches, bracelets, mobile phones, and tabletcomputers, and will not be elaborated here.

Other embodiments of this disclosure will be readily apparent to thoseskilled in the art from consideration of the specification and practiceof the application disclosed herein. This application is intended tocover any modification, use or adaptation of this disclosure, and thesemodifications, uses or adaptations follow the general principles of thisdisclosure and include common knowledge or conventional technical meansin the technical field not disclosed in this disclosure. Thespecification and embodiments are to be considered exemplary only, withthe actual scope and spirit of the disclosure being indicated by theappended claims.

1. A display panel, comprising: a driving backplane; a first electrodelayer, disposed on one side of the driving backplane and comprising aplurality of first electrodes distributed at intervals; a pixeldefinition layer, arranged on the side, same as the first electrodelayer, of the driving backplane and exposing each of the firstelectrodes, wherein the pixel definition layer comprises a filling layerand a cut-off layer stacked in a direction away from the drivingbackplane, the filling layer has a thickness smaller than the firstelectrode layer and is located outside the first electrodes, the cut-offlayer is provided with a separation slot located outside the firstelectrodes, and a first cut-off slot is provided on a sidewall of theseparation slot; a light-emitting layer, covering the cut-off layer andthe first electrode layer; and a second electrode, covering thelight-emitting layer.
 2. The display panel according to claim 1, whereinthe cut-off layer comprises a plurality of insulating layers stacked inthe direction away from the driving backplane, the separation slotexposes the filling layer, the first cut-off slot is provided in aninsulating layer of the insulating layers, and the insulating layerwhere the first cut-off slot is located is any insulating layer otherthan an insulating layer farthest from the driving backplane.
 3. Thedisplay panel according to claim 1, wherein the insulating layers of thecut-off layer comprise a first insulating layer, a second insulatinglayer and a third insulating layer stacked in sequence along thedirection away from the driving backplane, and the first cut-off slot isprovided in the second insulating layer.
 4. The display panel accordingto claim 3, wherein the sidewall of the separation slot is a slopesurface expanding in the direction away from the driving backplane. 5.The display panel according to claim 4, wherein a bottom surface of thefirst cut-off slot is a slope surface with decreasing depths in thedirection away from the driving backplane.
 6. The display panelaccording to claim 5, wherein a slope angle of the bottom surface of thefirst cut-off slot is larger than a slope angle of the sidewall of theseparation slot located on the first insulating layer, and larger than aslope angle of the sidewall of the separation slot located on the thirdinsulating layer.
 7. The display panel according to claim 5, wherein asum of a slope angle of the bottom surface of the first cut-off slot anda slope angle of the sidewall of the separation slot located on thefirst insulating layer is not greater than 90°; or wherein a sum of aslope angle of the bottom surface of the first cut-off slot and a slopeangle of the sidewall of the separation slot located on the thirdinsulating layer is not greater than 90°.
 8. (canceled)
 9. The displaypanel according to claim 4, wherein an included angle between extendingsurfaces of two sidewalls of the separation slot is an acute angle. 10.The display panel according to claim 5, wherein the cut-off layercomprises a cut-off portion and an extension portion, the cut-offportion is located outside the first electrodes, the extension portionis located on a surface of the first electrodes away from the drivingbackplane and has a pixel opening exposing the first electrodes, and asidewall of the pixel opening is a slope surface expanding in thedirection away from the driving backplane.
 11. The display panelaccording to claim 10, wherein a sum of a slope angle of the sidewall ofthe pixel opening and a slope angle of the bottom surface of the firstcut-off slot is not greater than 90°.
 12. The display panel according toclaim 10, wherein the sidewall of at least a part of the pixel openingis provided with a second cut-off slot.
 13. The display panel accordingto claim 12, wherein a maximum depth of the first cut-off slot isgreater than a maximum depth of the second cut-off slot.
 14. The displaypanel according to claim 13, wherein a part of the third insulatinglayer used for forming a sidewall of the first cut-off slot is inclinedto the driving backplane at a first inclination angle; a part of thethird insulating layer used for forming a sidewall of the second cut-offslot is inclined to the driving backplane at a second inclination angle;and the first inclination angle is greater than the second inclinationangle.
 15. The display panel according to claim 1, wherein aplanarization portion is formed in a region of the second electrodecorresponding to the first electrodes, and a groove portion is formed ina region of the second electrode corresponding to the separation slot,and a smooth transition is present between the planarization portion andthe groove portion.
 16. The display panel according to claim 15, whereina depth of the groove portion is less than a depth of the separationslot; or wherein the depth of the groove portion is greater than thethickness of the filling layer. 17-18. (canceled)
 19. The display panelaccording to claim 15, wherein the light-emitting layer furthercomprises a plurality of light-emitting sub-layers connected in series,at least one of the light-emitting sub-layers is connected in serieswith an adjacent one of the light-emitting sub-layers through a chargegeneration layer, and a part of the charge generation layercorresponding to the first electrodes is discontinuous with a part ofthe charge generation layer corresponding to the separation slot. 20.The display panel according to claim 1, wherein the filling layer is incontact with a sidewall of the first electrodes, or wherein the fillinglayer comprises a filling insulating layer and a filling conductivelayer stacked in the direction away from the driving backplane, thefilling insulating layer is in contact with the sidewall of the firstelectrodes, and the filling conductive layer is spaced apart from thesidewall of the first electrodes.
 21. The display panel according toclaim 20, wherein the driving backplane comprises a pixel area and aperipheral area outside the pixel area, the pixel area is provided witha pixel circuit used for driving light emission of the light-emittinglayer, and the peripheral area is provided with a peripheral circuit;the first electrode layer further comprises an adapter ring, anorthographic projection of the adapter ring on the driving backplane islocated in the peripheral area and surrounds the pixel area, the adapterring is connected with the peripheral circuit, the second electrode isconnected with the adapter ring, and the adapter ring is provided with anotch; the filling conductive layer comprises a main body and aconnecting portion, the main body is located within the adapter ring andis spaced apart from the adapter ring; the connecting portion isconnected with the main body, passes out of the adapter ring through thenotch, is spaced apart from the adapter ring, and is used for receivingan aging voltage signal.
 22. A method for manufacturing the displaypanel according to claim 20, comprising: forming the driving backplane;forming, on a side of the driving backplane, the first electrode layercomprising the plurality of first electrodes distributed at intervals;forming, on the side of the driving backplane provided with the firstelectrode layer, the pixel definition layer exposing each of the firstelectrodes, wherein the pixel definition layer comprises a filling layerand a cut-off layer stacked in a direction away from the drivingbackplane, the filling layer has a thickness smaller than the firstelectrode layer and is located outside the first electrodes; applying,for a specified period of time, an aging voltage signal to the fillingconductive layer; forming, at the cut-off layer, the separation slotlocated outside the first electrodes and the first cut-off slot locatedon a sidewall of the separation slot; forming the light-emitting layercovering the cut-off layer and the first electrode layer; and formingthe second electrode covering the light-emitting layer.
 23. A displaydevice, comprising a display panel, wherein the display panel comprises:a driving backplane; a first electrode layer, disposed on one side ofthe driving backplane and comprising a plurality of first electrodesdistributed at intervals; a pixel definition layer, arranged on theside, same as the first electrode layer, of the driving backplane andexposing each of the first electrodes, wherein the pixel definitionlayer comprises a filling layer and a cut-off layer stacked in adirection away from the driving backplane, the filling layer has athickness smaller than the first electrode layer and is located outsidethe first electrodes, the cut-off layer is provided with a separationslot located outside the first electrodes, and a first cut-off slot isprovided on a sidewall of the separation slot; a light-emitting layer,covering the cut-off layer and the first electrode layer; and a secondelectrode, covering the light-emitting layer.